The present invention relates to a reproduced signal processing technology and a magrnetic recording technology, and in particular, to a reproduced signal processing technology and a magnetic recording technology which are highly resistive in a data signal region against noises and the like associated with reduction in amplitude of the reproduced signal and the like due to thermal asperity and defects on a disk medium which are problems in a narrow spacing operation in a magnetic disk unit or the like using a magnetoresistive (MR) head as its reproducing head.
FIG. 7 shows constitution of an interface section of magnetic heads 1 and 2 of a magnetic disk unit. As a reproducing head 3, a magnetoresistive head is used in this configuration. The MR head 3 is a thin film head in which a thin film element having magnetoresistance effect is used as a sensor. When spacing between the MR head and the disk becomes small, there may occur a case in which, for example, the MR head 3 is brought into contact with a small projection of the disk and hence the value of resistance of the MR head varies due to heat generated by friction therebetween. It has been known that this leads to thermal asperity (TA) in which an envelope of the signal considerably undulates or deforms due to the change in the resistance value as shown in FIG. 8. A magnitude (Ata) of thermal asperity possibly becomes equal to or more than that of a signal amplitude (Asig). Therefore, when there appears thermal asperity, the data reproducing performance is fatally damaged. Furthermore, when a small defect (peeling of a magnetic film or the likes) 5 exists on a disk medium in FIG. 7, the amplitude of the signal is lowered as shown in FIG. 9, and signals are lost in worst situations depending on cases. Consequently, presence of a defect on the medium possibly exerts a fatal influence onto the data reproducing performance.
FIG. 10 shows an example of constitution of a magnetic disk drive (HDD) 10. The HDD 10 includes a head disk assembly (HDA) 20 including a magnetic disk 2, a magnetic head 1, a carriage 11, a read/write IC 12 mounted on the carriage 11, a spindle motor 13, and a flexible package (FPC) 14 on which signal paths are printed and a package board (PCB) 30 including a signal processing LSI (SPC) chip 21, a hard disk controller (HDC) 22, a servo controller (SRVC) 23, a microprocessor (MP) 24, an SCSI chip 25, a read-only memory (ROM) 26, and a random access memory (RAM) 27.
Description will now be given of a flow of a data reproduced signal. The reproduced signal from the MR head 3 is amplified by a pre-amplifier of an MR head in the read/write integrated circuit chip (R/W IC) 12 on the carriage 11 and is fed through a pattern wiring on the FPC 14 to be inputted to the package board (PCB) 30. This signal is inputted to a reproducing circuit (RSPC) 201 in the signal processing LSI (SPC) chip 21. The reproducing circuit 201 discriminates the reproduced signal to resultantly output digital data via an interface circuit 202 to the hard disk controller (HDC) 22. The HDC 22 includes therein an error correction circuit (ECC) to correct any error in the reproduced data inputted from the SPC 21, and if necessary, the HDC 22 retries the data reproduction. The reproduced data outputted from the HDC 22 is outputted via the SCSI chip 25 to the host computer. Incidentally, 202 indicates an interface circuit (IF) for the HDC 22 and 203 denotes a recording circuit (WSPC) including a modulating circuit or an encoder and the like.
FIG. 11 shows an example of structure of the reproducing circuit (RSPC) 201. Applied to this example is a data signal processing technology of "partial response+maximum likelihood decoding (PRML)" or "extended partial response+maximum likelihood decoding (PRML)". The example of the signal processing circuit includes a variable gain amplifier (VGA) 211, an analog equalizer (AEQ) 212 having a low-pass filter characteristic and a high-pass boost characteristic, an analog-to-digital (A/D) converter (ADC) 213, a digital equalizer (DEQ) 214, a maximum likelihood detector (ML) 215, a sync byte detector (SBD) 217, a decoder (DEC) 216, and a de-scrambler (DSC) 218; a variable gain amplifier controller (VGC) 230 for controlling a gain of the VGA 211 at data reproduction, a voltage controlled oscillator (VCO) 219 for supplying a sampling clock signal to the ADC, and a VCO controller (VCOC) 220. In this example, reproduced data is outputted to the HDC 22.
The VGAC 230 includes in many cases an analog VGAC (AVGAC) 231 which detects an amplitude of the analog output signal from the AEQ 212 and controls the gain of the VGA 211 to bring the amplitude close to a target amplitude at a high speed and a digital VGAC (DVGAC) 232 which controls the gain of the VGA 211 to bring digital data outputted from the DEQ 214 close to a target value so that the digital data follows the target value.
The VCOC 220 includes an analog TCOC (AVCOC) 221 which compares a phase and a frequency of a pulse generated from the analog output signal from the AEQ 212 with those of the sampling clock signal from the VCO 219 to conduct a high-speed capturing so as to establish synchronization of the frequency and the phase between the sampling clock signal and the analog output signal and a digital VCOC (DVCOC) 222 which detects a phase difference from digital data outputted from the DEQ 214 to minimize the phase difference. Alternatively, the VCOC 220 includes only a DVCOC 222 depending on cases. In the explanation below, a closed loop including the VGA211, AEQ 212, ADC 213, DEQ 214, and VGAC 230 is referred to as an automatic gain control (AGC) loop 233. Additionally, a closed loop including the VCO 219, ADC 213, DEQ 214, and VCOC 220 is referred to as a phase locked loop (PLL) 223.
Operation of the reproducing circuit (RSPC) 201 will be described. The VGA 211 receives as its input a signal amplified by the R/W IC 12 to a certain amplitude and amplifies the input signal to obtain an output signal so as to bring an amplitude of the output signal close to a target amplitude in an input to the maximum likelihood detector (ML) 215. In this operation, the VGAC 230 controls the VGA 211. The AEQ 212 receives as its input an output signal from the VGA 211 to conduct removal of noise in an unnecessary band, a pre-equalization, and the like. The ADC 213 converts the analog output signal from the AEQ 212 into a digital signal. In this case, the sampling clock of the ADC 213 is controlled such that a sequence of sample signal values of the input to the ML detector 215 is within a target amplitude. For this purpose, the VCOC 220 controls the control voltage of the VCO 219. The DEQ 214 conducts waveform equalization for the output data from the ADC 213 so that the ML detector 215 easily discriminates signals. The ML deflector 215 discriminates high-level and low-level signals of output data from the DEQ 214 to produce binary data. When the SBD 217 detects a sync byte indicating a start point of data in the output data from the ML detector 215, the DEC 216 decodes the data beginning at the point. The data is de-scrambled by the DSC 218 and then undergoes; a serial-to-parallel conversion, and resultant user data is outputted to the HDC 22.
When a signal waveform including thermal asperity is inputted to the reproducing circuit (RSPC) 201, there possibly occur two kinds of data errors. First, the signal waveform itself varies or deforms and hence a data discrimination error is detested in the ML detector 215. Primary reasons for the variation in the signal waveform are as follows. A signal exceeding a dynamic range due to thermal asperity is inputted to the A/D converter 213 and the output therefrom saturates in either one of the polarity directions (i.e., positive or negative side), which prevents the waveformn equalization in the digital equalizer 214. The data discrimination error can be recovered by increasing the correction performance of the error correction circuit (ECC) in the hard disk controller 22 of FIG. 10 to enable an error correction of data having a longer data length. Simultaneously, the error can be saved or recovered by decreasing the period for the saturation in the A/D converter 213 due to thermal asperity to shorten the data error length to a range in which the ECC can correct the data error. Second, the AGC and PLL loops become out of order in operation and hence there occurs a data burst error. Main reasons for the disorder in operation of the AGC and PLL loops are as follows. The control quantities of the VGAC 230 and the VCOC 220 are disturbed for a long period of variation in the envelope of waveform due to thermal asperity and hence wrong control quantities are fed back to the VGA 211 and the VCO 219. Specifically, the control quantities are fed back thereto such that the VGAC 230 controls the amplitude to be reduced and the VCOC 220 controls the frequency to be lowered so as to delay the phase. The data burst error possibly leads to a long error length and the error cannot be corrected by the ECC; moreover, the data cannot be recovered through the correction retry in some cases, leading to a device failure. Consequently, there is essentially required to take a countermeasure against thermal asperity to keep the normal operation in the AGC and PLL loops.
Next, when a signal waveform having an amplitude reduced by a medium defect is inputted to the reproducing circuit (RSPC) 201, there also take place two kinds of data errors as in the case of thermal asperity. First, the signal waveform itself varies and hence a data discrimination error is detected by the ML detector 215. This error can be recovered by increasing the correction performance of the error correction circuit in the hard disk controller 22 of FIG. 10. Second, the AGC and PLL loops become out of order in operation and hence a data burst error occurs. Main reasons for the disorder in the AGC and PLL loops are as follows. The control quantities of the VGAC 230 and the VCOC 220 are disturbed during a period in which the signal amplitude is lowered and wrong control quantities are fed back to the VGA 211 and the VCO 219. Specifically, the control quantities are fed back thereto such that the VGAC 217 increases the amplitude and the VCOC 220 decreases the frequency to delay the phase. The data burst error possibly leads to a long error length and the error cannot be corrected by the ECC. Moreover, the data cannot be recovered through the correction retry in some cases, leading to a device failure. Consequently, there is essentially required to take a countermeasure against the decrease in the signal amplitude due to a medium defect to keep the normal operation in the AGC and PLL loops.
Description will now be given of an example of a thermal asperity compensation method and operation in accordance with the prior art. The prior art has been described in, for example, U.S. Pat. No. 4,914,398, JP-B-7-86964, and JP-A-6-28785.
In short, in accordance with U.S. Pat. No. 4,914,398 and JP-B-7-86964, there is disclosed a first method in which a noise due to thermal asperity is detected by an analog circuit procedure such that the noise is subtracted from a reproduced signal to thereby removing on the fly the noise related to thermal asperity.
Additionally, in accordance with JP-A-6-28785, there is disclosed a second method in which when conducting a retry for a data read error, thermal asperity is detected in accordance with the number of saturated samples in the A/D converter to minimize the target amplitude of the digital equalizer so as to prevent saturation in the A/D converter. Namely, the cutoff frequency of the low band is increased in the reproducing circuit to shorten the period of influence of the noise due to thermal asperity; moreover, the AGC and PLL loops are held at the same time.
However, in the first method, the analog circuit becomes very great in size; moreover, in operation of the removal circuit, the performance is deteriorated by a noise generated by the removal circuit. In the second method, the operation cannot be conducted on the fly and hence the performance of the apparatus inevitably occurs when thermal asperity appears.
Moreover, when the AGC and PLL loops have a high loop gain, the control quantities of the VGAC 230 and the VCOC 220 are considerably disturbed during a period of several bits from when thermal asperity occurs to when the thermal asperity detector holds the AGC and PLL loops. Even when the noise due to thermal asperity is removed, the AGC and PLL cannot be put to a desired operation and there may occur a burst error. The prior art has no concern about a thermal asperity but also about a problem in which the waveform having a signal amplitude lowered due to a medium defect, not only by thermal asperity, cannot be coped with.